Europe’s chip future is being built in real time, and the view from Munich is electric. We sit down with IMEC’s leadership and ESMC’s founding CEO to unpack how pilot lines, a major Dresden fab, and the EU Chips Act are reshaping the continent’s strategy—from research to high-volume manufacturing. Along the way, we track the evolution of Semicon Europa over 50 years, from a supplier-centric expo to a convening force that brings equipment makers, materials leaders, device companies, and end users into one space.

Our guests open the hood on what resilience actually looks like: a 28 nm to 12 nm FinFET roadmap with integrated RRAM for microcontrollers, a half‑million‑wafers‑per‑year target, and a hiring plan that scales with purpose-built training in Dresden and Taiwan. On the R&D front, IMEC’s expanded pilot line infrastructure—fueled by multi‑billion‑euro investment—helps Europe retain technology leadership while translating breakthroughs into products. We also examine advanced packaging, where 3D integration and chiplet architectures blur the line between front end and back end and create fresh opportunities for automotive and industrial electronics.

The conversation gets candid on sovereignty versus interdependence. Full autarky is a myth; durable relevance comes from global collaboration, reverse dependencies, and focus on areas where Europe is indispensable—lithography, metrology, materials, and increasingly packaging and system design. We talk talent, too: why workforce visibility, skills pipelines, and on-the-job training will determine whether ambitious ramps hit their marks. If you care about semiconductors, policy, and the future of manufacturing in Europe, this is your inside track.

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A crowded server board with ten thousand parts doesn’t forgive sloppy inspection—and neither do pricey GPUs and chiplets. From the floor of Productronica in Munich, we dig into how automated optical inspection keeps advanced packages honest once they hit the PCB line, where solder quality, coplanarity, and sheer component variety can make or break yield. Vidya Vijay from Nordson Test & Inspection joins us to unpack why AOI remains the fastest path to actionable insight, when X‑ray is the smarter choice, and how new sensor design changes the game for reflective, high‑mix assemblies.

We explore the real pain points engineers face today: shiny dies that confuse cameras, BGAs packed with I/O where hidden defects hide under the body, and miniature passives that crowd tight keep‑outs. Vidya explains how three‑phase profilometry creates true 3D height maps by projecting fringe patterns and reading them from multiple angles, enabling precise checks for corner fill, underfill, and coplanarity. We also get into multi‑reflection suppression, Nordson’s approach to filtering glare and ghost images so the system sees the joint, not the noise. With true RGB on side cameras and higher resolution, AOI can now pick out tiny solder balls and subtle surface issues at speed—fuel for stronger AI autoprogramming and more reliable defect classification.

If throughput is king, data is queen. We talk about closing the loop from inspection back to the line to prevent bad lots—flagging stencil drift, placement offsets, and paste issues before they explode into scrap. Then we spotlight Nordson's launched SQ5000 Pro: faster cycle times, a wider field of view, and configurable 7 µm or 10 µm sensors designed for modern PCBA demands. Whether you’re chasing yield on high‑value GPUs or balancing AOI with AXI on dense boards, this conversation offers a practical roadmap for choosing the right tool, tackling reflectivity, and using insight to drive predictable quality.

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Delivering best-in-class test, inspection, and metrology solutions for semiconductor applications.

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Want a candid look at how women build durable careers in one of the world’s toughest industries? We sit down with three semiconductor leaders - Nitza Basoco, Anne Meixner and Julia Freer - who share how early encouragement, gritty problem solving, and clear communication turned curiosity into impact. From summer jobs at national labs and early days at IBM to leading operations, test, and sustainability initiatives, their stories show why diverse voices aren’t just nice to have—they’re a competitive advantage.

We dig into the real moments: being the only woman in a test engineering group, pushing for inclusive language that actually changes culture, and navigating career pivots to balance family, flexibility, and ambition. You’ll hear how mentorship and sponsorship differ—and why you need both—plus specific tactics to make them work inside fast-moving chip companies. One unforgettable segment starts with a five-minute crash-and-burn presentation and becomes a two-year, teamwide communication overhaul that turns shy engineers into confident presenters ready for conferences and boardrooms.

Across materials science, advanced packaging, test and inspection, and sustainability, the thread is clear: communication is a core engineering skill. Writing reflective status reports, designing slides for decisions, and telling a tight technical story can accelerate yield improvements, align manufacturing and supply chain, and win executive support. We also tackle today’s DEI headwinds with a practical lens—keep the pipeline alive, promote from within, and build programs that outlast policy shifts. The conversation closes with why their new book matters: ordinary, relatable role models who show many valid paths into STEM and semiconductors.

Learn more about the book, Empowering Women in STEM. 

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Teradyne test solutions for semiconductors lets customers consistently meet their quality standards.

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Power electronics are quietly rewriting the rules of energy use—from the range of your EV to the efficiency of a hyperscale data center. Françoise sits down with Henkel’s Ram Trichur to unpack what’s driving the $67.5B surge in power semiconductors and why the move to wide bandgap materials like silicon carbide and gallium nitride is such a big deal. 

We break down the real differences between logic and power devices, then dive into where innovation is happening right now: die attach materials, thermal pathways, and manufacturing processes that can keep up with higher power densities. Ram explains why traditional wirebond packaging remains dominant in power, even as modules climb from 400 V to 800 V and beyond. You’ll learn how the industry is moving from solder to silver sintering for performance, and why copper-based sintering may be the breakthrough that balances cost, reliability, and manufacturability.

From discrete devices to full power modules, we explore the challenges of thinner die, copper leadframes, backside metallization compatibility, and bond line control. Ram shares Henkel’s roadmap for pressure-assisted copper sintering at lower temperatures and pressures in nitrogen, the multi-year qualification path customers expect, and how early sampling shortens time to scale. If you care about EV range, charger efficiency, industrial uptime, or greener data centers, this conversation connects the dots between materials science, packaging engineering, and system-level performance.

If you enjoyed this deep dive, follow the show, share it with a colleague who cares about SiC and GaN, and leave a quick review to help others find us. Got a question or a hot take on copper vs. silver sintering? Drop us a note and join the conversation.

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Henke's advanced materials elevate semiconductor packaging to meet power, performance, area and cost

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The floor in Phoenix was packed, and so were the ideas. We sat down with innovators across the stack—equipment makers, metrology experts, logistics strategists, and software leaders—to map the real state of advanced packaging and what it takes to build, measure, move, and power tomorrow’s chips.

EV Group kicked things off with a candid look at die-to-wafer realities: activation on film frame, then 100% overlay metrology that measures tens of thousands of points per hour so every die and corner is verified. They also unveiled LithoScale XT, a fully digital, maskless lithography system printing 300 mm at 60 wph—perfect for massive AI dies and fast design turns. 

Lab14 widened the frame with a portfolio approach: direct-write lithography, single-wafer processing, data prep, and analysis tools working as a coordinated line, with data sharing and AI feedback baked in.

Resilience and regionalization came to life through Kuehne+Nagel’s on-the-ground view: supplier clustering near fabs, cross-border trucking, time-critical services, and 4PL integration that gives real-time visibility and smarter capacity planning. 

ERS showed where throughput meets cost: photothermal debonding with lower stress and reusable glass carriers, demo centers in Taiwan (and planned in North America), plus surge demand for warpage repair as volumes rise.

Process control is moving into packaging with front-end rigor. Nova detailed metrology for hybrid bonding, chemistry monitoring of plating baths, X-ray and XPS/SIMS material insights, and the handling know-how to measure framed wafers and panels reliably. 

Nordson Test & Inspection highlighted AI-driven inspection, ultra-fast acoustic scanning, automated X-ray metrology, and sensor wafers that cut tool downtime and sharpen process windows. Comet showcased its CT and CA20 upgrades for 3D IC and TSV analysis.

Power dominated the later conversations. Siemens argued we need to design for energy from the chip through the blade, rack, and data center, simulating real workloads and cooling to slash gigawatts—then extend that thinking into the fab, where optimizing chillers and facilities already saves serious money. 

Onto Innovation brought it home with execution: the PACE Center now hosts partners’ tools, accelerating experiments for glass, TGV, and panel processes without waiting on public funds.

If you care about hybrid bonding, maskless lithography, CT for 3D ICs, panel-scale packaging, or cutting AI’s energy bill, this one is dense with takeaways and hard truths. Subscribe, share with a colleague who lives in the fab or data center, and leave a review telling us which insight you’ll act on first.

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A nationwide talent engine for chips is taking shape—and it’s built to scale. Recorded live at SEMICON West in Phoenix, we sit down with SEMI Foundation leaders to unpack the National Network for Microelectronics Education, a hub-and-node model designed to align schools, employers, and workforce systems. Backed by CHIPS Act funding through the National Science Foundation, NNME will fund multi-state regional nodes that modernize curricula, streamline upskilling, and share proven playbooks across the country. We also unveil the refreshed Chip Path portal, which maps your skills and interests to real jobs in fabs, equipment, and materials, and we highlight SEMI-Quest, a hands-on STEM experience designed to spark early curiosity about microelectronics.

Then we turn to sustainability where momentum is accelerating. The Semiconductor Climate Consortium has grown past 100 members and is shifting from baselines to projects that deliver measurable impact. We explore how the Energy Collaborative pushes for policy that opens affordable renewable power, while SCC advances user-side strategies—better emissions accounting, renewable procurement models, and fab energy efficiency. A core challenge emerges: hyperscalers often target net zero by 2030, while many chipmakers point to 2050. We dig into how coordinated innovation, shared standards, and advocacy can close that 20-year gap.

AI’s energy appetite raises the stakes, so we tackle both sides of the equation: adding clean capacity where it matters most and designing for lower power at the chip and fab level. From global cooperation across APAC, EU, and the U.S. to practical ways individuals and companies can act now, the throughline is collaboration with urgency. Ready to find your role in the future of chips—whether building skills, hiring smarter, or decarbonizing faster? Subscribe, share this episode with your team, and leave a review to help more people find these insights.

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A global association, SEMI represents the entire electronics manufacturing and design supply chain.

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We recorded live at IMAPS with Siemens, ACM Research, Shellback Semiconductor, DECA, Nordson Electronic Solutions, and VIEW Micro Metrology to explore how AI demand, chiplets, and panels are reshaping advanced packaging. We dig into 3D BLOX, thermal and test roadblocks, green chemistries, metrology at scale, and why the back end now leads innovation. Listen to learn about:

• The Siemens–ASE collaboration on 3D BLOX models and VIPACK workflows
• Interoperable YAML-based packaging definitions moving toward IEEE standard
• 3D stacking to cut picojoules per bit amid thermal and test limits
• Panel-level packaging economics, sizes, and lack of standards
• ACM Research updates in copper plating, bevel clean, frame clean, and compound deplating
• Batch spray versus single wafer trade-offs at Shellback Semiconductor
• HydrOzone green strip replacing legacy NMP in select flows
•The  DECA–SST deal for NVM chiplet package and SoC disaggregation
• Nordson Electronic Solutions' panel strategy, IntelliJet 1.1, Vantage platform, and warpage control
• VIEW Micro Metrology's high-throughput telecentric metrology across wafers and large panels

Learn more at imaps.org

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We record live at IMAPS to follow a first-time attendee’s leap into advanced packaging and a trio of high school students discovering semiconductors, robotics, and career paths that bridge disciplines. Along the way, we unpack speed-to-market, standards, hybrid vs TCB, and why AI skills matter.

• why a self-funded first conference can reset a career
• key takeaways from PDCs and technical talks
• time-to-market pressure across packaging workflows
• standards tension between front-end and packaging
• hybrid bonding promise versus TCB workhorse reality
• how to network with intent and follow through
• volunteering with IMAPS to build early-career hubs
• robotics as an on-ramp to semiconductors
• interdisciplinary routes into microelectronics
• student goals, mentors, and university paths
• practical questions to ask on the expo floor

IMAPS International
IMAPS is the largest society dedicated to microelectronics and electronics packaging advancement.

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We sit down with Dr. Subu Iyer of UCLA to unpack chiplets vs dielets, why a universal ecosystem is missing, and how sub‑10 µm bump pitch could make protocols optional. Then we host a panel featuring John Knickerbocker, IBM; Mike Kelly, Amkor; and Tolga Tekin, Fraunhofer IZM on co‑packaged optics, bandwidth, and power for AI data centers.

• chiplet as design construct, dielet as physical die
• lack of universal chiplet ecosystem and interoperability
• bump pitch scaling and protocol overhead trade‑offs
• packaging purpose reframed as power, communication, and cooling
• economic shift and value capture in advanced packaging
• national competitiveness, prototyping access, and talent pipeline
• co‑packaged optics definition, drivers, and cost targets
• copper reach limits, latency, and bandwidth density for AI
• hyperscalers as early adopters and five‑year outlook

Learn more at imaps.org

IMAPS International
IMAPS is the largest society dedicated to microelectronics and electronics packaging advancement.

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A semiconductor wafer travels around the globe five times on average before becoming the chip in your smartphone. Each journey represents a potential risk to device reliability that few consumers—or even industry professionals—ever consider.

Behind every high-performing semiconductor device lies a carefully orchestrated logistics operation ensuring these sensitive components arrive intact and functioning. As Francoise von Trapp discovers in this eye-opening conversation with John Desmond and Valentina Aplenalp of Kuehne+Nagel, the journey matters just as much as the manufacturing.

Drawing from his background in semiconductor design and manufacturing, John explains how vibration, temperature fluctuations, humidity, and even light exposure can compromise device integrity during transit. Wafers transported in specialized containers called FOUPs, delicate packaging materials, and critical replacement parts for manufacturing equipment all require extraordinary care throughout their global journeys.

Valentina reveals the sophisticated systems developed to protect these valuable shipments: real-time environmental monitoring sensors connected to 24/7 control towers, specialized air-ride vehicles, and climate-controlled packaging solutions. When emergencies arise—like a critical equipment failure threatening production—their time-critical logistics teams deliver replacement parts within hours, not days.

Most fascinating is the human element. The Semicon Chain certification program ensures every person who might handle semiconductor shipments receives specialized training, creating an end-to-end system where nothing is left to chance. As John puts it, they aim to be "the best partner that you never know you had"—the hidden force ensuring semiconductor reliability.

Whether you're a semiconductor professional, supply chain specialist, or simply curious about the invisible infrastructure supporting our digital world, this episode offers rare insight into how logistics enables technological innovation. 

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SEMI's flagship event, SEMICON West, is moving to Phoenix, Arizona this October 7-9, 2025, after 35 years in San Francisco, coinciding with the region's semiconductor manufacturing boom and $200 billion in announced investments. In this episode, Françoise speaks with SEMI Americas president, Joe Stockunas, who shares reasons for the move and what attendees can expect to experience. This includes: 

• Move driven by need to refresh the event and bring it closer to industry growth
• New October timing based on attendee feedback to avoid disrupting July holidays
• CEO Summit featuring keynotes from Arizona Governor Hobbs, TSMC, NVIDIA, and Intel
• Exhibition floor expanding to over 1,500 booths (50% increase from last year)
• Technical tracks focused on advanced packaging, AI, cybersecurity, and workforce development
• Street fair networking event Tuesday evening on 3rd Street
• Student attendance expected to jump from 700 to 7,000 thanks to proximity to Arizona's educational institutions
• Special SemiQuest exhibit at Arizona Science Museum running September through year-end
• Global Semicon events continue growing, with Semicon India doubling to 1,000 booths

For registration and complete program information, visit semiconwest.org or download the event app to navigate the show and build your agenda.

SEMI
A global association, SEMI represents the entire electronics manufacturing and design supply chain.

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The IMAPS International Symposium returns to the Town & Country Resort in San Diego from September 29-October 2, 2024, featuring restructured technical tracks, new Monday panel discussions, and exciting networking events including a special reception aboard the USS Midway aircraft carrier. General Chair Benson Chan and outgoing IMAPS President Erica Folk share what attendees can expect at this premier microelectronics packaging event.

• Expanded program with six focused technical tracks for better attendee experience
• New Monday afternoon panels on thermal challenges, HIR roadmap, and co-packaged optics
• Co-location with the new Thermal Management Conference (Wednesday-Friday)
• Special reception on the USS Midway aircraft carrier (requires RSVP during registration)
• Student engagement through high school tours, university booths, and the Posters & Pizza session
• Leadership transition as Erica Folk hands the presidency to Dan Kruger
• Multiple networking opportunities throughout the week including the Exhibitor Happy Hour
• Volunteer opportunities that provide valuable professional development and career connections

Register now at imaps.org to secure your spot at the symposium and don't forget to RSVP for the special Midway reception.

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X-ray technology reveals what the naked eye cannot see - the intricate world of semiconductor interconnects that power our digital lives. In this deep dive with Ben Peecock, Senior Director of Business Development at Nordson Test and Inspection, we uncover the critical differences between x-ray inspection and metrology that keep semiconductor manufacturing on track.

With nearly three decades of experience in the industry, Peecock guides us through the evolution of semiconductor inspection technologies. While silicon itself remains transparent to x-rays, the metal interconnects between components provide the perfect canvas for quality assessment. As advanced packaging pushes toward smaller, more complex structures with 3D stacking and chiplet architectures, the need for sophisticated inspection has never been greater.

We explore how inspection (focused on imagery) and metrology (centered on precise measurements) serve complementary roles across the semiconductor manufacturing ecosystem. From R&D laboratories perfecting new processes to high-volume production lines seeking zero defects, these technologies help manufacturers identify issues before they become costly failures. The conversation ventures into the distinctions between 2D inspection (optimized for speed) and 3D analysis (delivering comprehensive structural information) and when each approach proves most valuable.

Particularly fascinating is Nordson's approach to vertical integration, developing their own specialized x-ray sources and detectors optimized specifically for semiconductor applications. This expertise extends to their innovative work integrating artificial intelligence to accelerate inspections while maintaining accuracy. Their thoughtful approach to data security gives customers options to protect proprietary information while still benefiting from AI's capabilities.

Discover how these technologies are already supporting emerging trends like panel-level packaging and learn about Nordson's unique radiation management solutions that protect sensitive components during inspection. Whether you're a semiconductor professional seeking quality control insights or simply curious about the technologies that ensure your electronic devices function reliably, this episode offers a fascinating glimpse into an invisible world of quality assurance.

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Delivering best-in-class test, inspection, and metrology solutions for semiconductor applications.

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Thailand is positioning itself as a new hotspot for semiconductor and microelectronics manufacturing, building on existing infrastructure and establishing key partnerships throughout the region. Managing editor Jillian McNichol shares insights from her recent trip to Thailand where she toured facilities and interviewed industry leaders about the country's ambitious plans.

• Thailand has been involved in assembly and test operations since 1996 through the Thai Microelectronics Center
• Currently Thailand is the 10th largest automobile exporter in the world, with a strong focus on power electronics
• Tariffs present significant challenges, with Thailand currently facing a 36% tariff rate for exports to the US
• The Eastern Economic Corridor (EEC) is a key region for manufacturing, with industrial parks, universities, and port facilities
• Sustainability is a major focus, with Thailand aiming for net zero emissions by 2050
• Thailand is addressing talent shortages through university partnerships that prepare graduates for industry needs
• Strong alignment between government, companies, and educational institutions is driving Thailand's semiconductor strategy.

Learn more in Jillian's article, Thailand: An Emerging Force in the Semiconductor Supply Chain.  

Learn more about the Thailand Board of Investment

Contact Jillian McNichol on LinkedIn

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The race toward more powerful AI carries a hidden cost that's becoming impossible to ignore: skyrocketing energy consumption. Did you know AI is projected to devour 10% of global electricity by 2030? This staggering figure has even forced tech giants to delay their sustainability goals.

Enter ASE's Executive Vice President Yin Chang, who reveals how the world's largest semiconductor packaging company is tackling this challenge head-on. The solution lies in revolutionary approaches to power delivery and data transmission. By integrating voltage regulators directly into substrates, power can be delivered mere nanometers from compute chips, drastically reducing energy loss. Even more promising is the shift from electrons to photons for data transmission, which slashes power consumption by an impressive 6x.

At the heart of these innovations is ASE's VI-PACK platform, a comprehensive toolbox that empowers system architects to create maximally efficient AI systems. Moving compute components closer together minimizes power requirements, while co-packaged optics enable the crucial electron-to-photon conversion for longer-distance communication. These technologies aren't just theoretical—industry leaders like NVIDIA and AMD are already implementing them, with significant efficiency improvements expected within five years.

The conversation extends beyond data centers to the future of AI at the edge. As foundry processes advance toward smaller nodes, the voltage requirements decrease, making AI more viable for battery-powered devices. Chang envisions a near future where personal devices run limited AI models locally, offering enhanced privacy by processing sensitive data without cloud dependencies.

Discover how advanced packaging is becoming the unsung hero in balancing our appetite for AI innovation with the planet's energy limitations. Follow ASE Global on LinkedIn or visit aseglobal.com to learn more about their pioneering work in sustainable semiconductor solutions.

Learn more at aseglobal.com or follow ASE Global on LinkedIn.

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ASE plays a significant role in the development of the world’s most innovative electronics.

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The 75th anniversary celebration of ECTC in Dallas showcases a remarkable evolution in advanced packaging technologies, revealing how semiconductor priorities have dramatically shifted. Rather than the relentless miniaturization of the smartphone era, today's AI-driven applications demand larger packages with more functionality and sophisticated thermal management solutions.

Glass core substrates emerged as the star technology of the conference, with standing-room-only sessions demonstrating the industry's intense interest in this promising material platform. The excitement is justified – glass offers superior dimensional stability and enables higher-density interconnects than traditional organic substrates. Meanwhile, co-packaged optics generated similar enthusiasm as engineers tackle the monumental challenge of powering AI server racks that consume between 0.5-1 megawatt each, making energy efficiency a critical concern.

Through conversations with industry leaders including Monita Pau (Onto Innovation), Charles Lee and Mark Gerber (ASE), Tim Olson (Deca),  Scott Sikorski (IBM), Roland Rettenmeier, (SCHMID Group), Simon McElrea (LDQX), Henan Zhang, (ACM Research), and Evelyn Weng (ERS Electronic) we gain insights into how these technologies will reshape semiconductor packaging.

With record attendance exceeding 2,500 participants, ECTC has firmly established itself as the premier venue for pre-competitive research in advanced packaging. The technologies showcased this year may take 5-10 years to reach high-volume manufacturing, but they provide a crucial window into the semiconductor industry's future direction. As one participant aptly noted, "We used to draw pictures of these advanced packaging technologies and people quite often laughed... now they are actually production products because it was the only way to get there."

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What happens when the world's thirst for artificial intelligence collides with physical limitations? The answer lies at the intersection of silicon innovation and packaging technology.

From the conference hall of ECTC 2025 in Dallas, we're joined by Sam Naffziger of AMD who reveals how AI has transformed from a peripheral topic to the dominant force in computing within just five years. The economic motivation is clear: creating machines that generate intelligence offers "uncalculable value" to humanity. Yet as Nafziger explains, today's large language models face significant limitations—they excel at pattern recognition but struggle with true reasoning, suffer from hallucinations, and require human verification for mission-critical applications.

Perhaps most surprising is Nafziger's revelation about "the data wall"—general-purpose AI models have essentially exhausted the high-quality training data available on the internet. This constraint is pushing AI development toward more sophisticated approaches involving reinforcement learning and models that check other models, gradually shifting from simple pattern recognition toward deliberative thinking that more closely resembles human reasoning.

The conversation tackles the looming concern of AI's energy consumption, projected to reach 10% of global power by 2030. Rather than viewing this as an insurmountable problem, Nafziger offers a compelling perspective: AI's ability to optimize countless processes—from transportation routing to crop yields and manufacturing efficiency—could ultimately lead to net energy savings despite its own substantial power requirements.

For the advanced packaging community, the message is clear: your work sits at the foundation of AI's future. As computational demands increase exponentially, innovations in thermal management, power delivery, and component integration will directly determine how quickly and effectively AI can evolve. 

Connect with Sam Naffziger on LinkedIn or visit AMD.com to learn more about their competitive AI solutions and join the conversation about technology that's reshaping our world.

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What happens when you gather 75 years of packaging innovation under one roof? The Electronic Component Technology Conference (ECTC) has transformed from a modest gathering of 300 electronics professionals to a powerhouse event attracting over 2,500 industry leaders, researchers, and visionaries. This remarkable journey reflects how advanced packaging has evolved from supporting technology to the driving force behind modern electronics.

In this special episode, we speak with three generations of ECTC committee members: Pat Thompson (with 41 years of ECTC experience), Przemek Gromala (10 years), and Florian Herault (since 2010). They share fascinating insights into how the conference has tracked—and often predicted—the industry's most significant shifts. From the days when Ball Grid Arrays were cutting-edge to today's excitement around hybrid bonding and chiplets, ECTC has been the barometer for packaging innovation.

The conversation reveals how technologies that once caused standing-room-only excitement have either become industry standards or faded into obscurity. Remember 450mm wafers? That path was abandoned in favor of panel-level packaging. Through-silicon vias struggled with cost issues for years before finding their sweet spot in high-performance applications. And the longstanding debate between System-on-Chip and System-in-Package approaches has evolved into today's heterogeneous integration paradigm.

Looking forward, our guests highlight the challenges driving tomorrow's innovations: thermal management for power-hungry AI chips, specialized edge computing architectures, and adapting advanced electronics to automotive and other harsh environments. As Host Françoise von Trapp observes, "It's a great time to be a nerd," with abundant technical challenges ensuring exciting work for packaging professionals for decades to come.

Don't miss our upcoming episode featuring ECTC keynote speaker Sam Naffziger discussing responsible AI implementation and the critical role of packaging in creating energy-efficient high-performance devices!

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Pratyush Kamal explains how 3DIC technologies are transforming semiconductor design as Moore's Law slows, requiring closer integration between chip and package design to maximize performance.

• Traditional chip design treated packaging as an afterthought with designers "throwing designs over the wall"
• Economic realities of advanced nodes mean companies now pay more for smaller transistors, driving chiplet adoption
• Thermal challenges multiply in 3D stacks as power density doubles with each added layer
• Data centers projected to consume 10% of US electricity by 2030, making power efficiency critical
• Siemens working to standardize design languages across tools and enable open chiplet ecosystems
• Average age of electrical engineers in US is 57, creating urgent need for workforce development
• Universal Chiplet Interconnect Express (UCIe) emerging as key standard for chiplet interoperability

Visit siemens.com/3DIC to learn more about Siemens' comprehensive 3DIC solutions.

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Siemens' EDA software helps you turn today's ideas into the sustainable products of the future.

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Andrew Mathers, Principal Product Line Manager at Nordson Test and Inspection, discusses the revolutionary advancements in 3D x-ray inspection technology and how they're improving semiconductor manufacturing quality.

• X-ray inspection requires high resolution, speed, and cost-effectiveness to drive better product quality
• Traditional 2D radiographic imaging is being replaced by 3D imaging for more stringent manufacturing requirements
• Planar CT imaging suffers from artifacts when inspecting flat electronic components like circuit boards and wafers
• Dynamic Planar CT takes more images from different angles with a wider field of view, reducing artifacts
• New technology operates twice as fast as traditional methods while reducing x-ray dose to sensitive components
• Automated inspection systems integrate directly into manufacturing lines with no human interaction required
• Common applications include detecting voids in ball grid arrays and micro bumps in flip chip devices
• The technology supports Quality 4.0 initiatives by providing feedback to improve manufacturing processes
• Nordson's systems are in use worldwide with an install base exceeding 2000 automated x-ray inspection systems

Learn more about Dynamic Planar CT and Nordson's x-ray inspection solutions at nordson.com or on their YouTube channel.

Nordson Test and Inspection
Delivering best-in-class test, inspection, and metrology solutions for semiconductor applications.

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The IEEE MTTS International Microwave Symposium attracts over 9,000 attendees and 500+ exhibitors to share cutting-edge developments in RF, microwave, and advanced packaging technologies. Tim Hancock and Jim Buckwalter from the IMS committee explain why this premier event, taking place in San Francisco's Moscone Center from June 15-20, has become increasingly relevant to professionals in advanced packaging and heterogeneous integration.

• Approximately 15% of accepted papers directly address packaging and heterogeneous integration topics
• Papers undergo rigorous double-blind review with an in-person committee meeting to ensure highest quality content
• Technical focus includes laminate technology, chip stacking, thermal management, and other critical packaging technologies
• Special workshops address 3D heterogeneous integration, millimeter-wave phased arrays, and advanced packaging solutions
• Exhibition floor features 500+ companies providing networking opportunities and technology discovery
• Student programs include design competitions, volunteer opportunities, and dedicated sessions for underrepresented groups
• Early bird registration ends May 16th with regular registration continuing at ims-ieee.org

Register at ims-ieee.org to secure your spot and book accommodations before they fill up.

THE 2025 IEEE MTT-S IMS
The 2025 IEEE MTT-S IMS is the largest event for RF and microwave professionals in the world.

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Acoustic inspection stands as a silent sentinel in semiconductor manufacturing, detecting microscopic defects that could lead to catastrophic failures in high-value applications. Bryan Schackmuth, Senior Product Line Manager at Nordson Test and Inspection, reveals how this technology has evolved from laboratory tools to production-line essentials.

When ultrasound encounters even the tiniest air gap—we're talking hundreds of angstroms—it reflects completely, making acoustic imaging uniquely powerful for evaluating bonds between materials. While optical inspection shows surface defects and X-ray reveals density variations, acoustic inspection peers between layers, identifying delamination and other hidden flaws that might otherwise escape detection until field failure.

The challenges of advanced packaging have driven significant innovation in acoustic inspection technology. As manufacturers stack more die, create complex interconnects, and push toward heterogeneous integration, the value of each wafer increases dramatically. Nordson's SpinSam system represents a breakthrough in this space, replacing traditional raster scanning with a rotational approach that achieves 41 wafers per hour—eight times faster than previous generation technology—while maintaining resolution down to 10 microns.

Beyond pure speed, the system's spinning scan technology offers unique advantages for edge inspection where defects are more common due to coefficient of thermal expansion effects. The modular design allows maintenance on individual scanners while others continue operating, maximizing uptime in production environments. Most exciting is the integration of AI and machine learning for defect detection, moving beyond simple thresholds to analyze complex multilayer images simultaneously.

Want to see how your inspection strategies might benefit from these advances? Check out Nordson's SpinSam technology at nordson.com and discover how acoustic inspection is helping manufacturers achieve higher yields and more reliable products in today's most demanding semiconductor applications.

Nordson Test and Inspection
Delivering best-in-class test, inspection, and metrology solutions for semiconductor applications.

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The 3D InCites Podcast celebrates microelectronics industry innovation with a special episode featuring this year's award winners in heterogeneous integration and chiplet technology.

• SallyAnn Henry, Jim Straus and David Wang, ACM Research, describe a horizontal rotation plating system for panel-level packaging with superior uniformity across square substrates
• Eric Gongora, of MacDermid Alpha, explains how NovaFab fine-grained copper enables hybrid bonding with customizable annealing times and improved electron migration resistance
• Chuck Woychik, NHanced Semiconductors, talks about how the company brings hybrid bonding capabilities onshore with expertise in wafer processing for both defense and commercial applications
• Keith Felton, Siemens Digital Industries Software, introduces Innovator 3DIC for hierarchical device planning that automatically propagates design changes throughout chiplet interfaces
• Kazuyuki Mitsukura explains how Resonac builds collaborative consortia in Japan and the US to solve complex advanced packaging challenges through shared resources
• Rex Anderson from Micross shares his engineering journey and passion for mentoring the next generation of technologists
• Ron Huemoeller and Eelco Bergman discuss how Saras Micro Devices addresses AI power challenges with embeddable S-Tile capacitors. They also talk about Saras corporate culture.

EV Group
EV Groups supplies high-volume equipment and process solutions for semiconductor manufacturing.

KLA, SPTS Division
KLA provides semiconductor equipment for metrology, inspection, wafer processing, and more.

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Navigating today's complex manufacturing landscape demands unprecedented supply chain resilience. This eye-opening conversation with Barry O'Dowd (Kuehne+Nagel) and Kamal Ahluwalia (Resilinc) reveals why robust supply chains matter more than ever—particularly for semiconductor capital equipment.

The semiconductor industry operates at extraordinary precision, with equipment working at scales as small as five nanometers—roughly 1/18,000th the width of a human hair. This precision makes these multi-million dollar tools exceptionally vulnerable during transport, requiring meticulous handling across tens of thousands of miles between manufacturing and installation. With leading-edge fabs costing up to $20 billion, equipment failures or delays can trigger catastrophic financial consequences.

Our experts explain how companies are reimagining resilience through sophisticated data analysis, multi-tier visibility, and proactive risk management. Barry shares how Kuehne+Nagel's risk mitigator tool brings together all supply chain stakeholders to identify vulnerabilities and implement mitigation strategies—expertise developed during their flawless delivery of over 2 billion COVID vaccines. Meanwhile, Kamal describes how Resilinc helps organizations leverage AI to anticipate disruptions across 40 different risk categories, from natural disasters to financial instability.

The conversation offers practical advice for strengthening your own supply chain: understand your end-to-end process, engage with experienced partners, and adopt a first-principles approach to reimagining resilience with current technology. As global uncertainties continue mounting—from geopolitical tensions to extreme weather events—supply chain resilience isn't merely about risk avoidance; it's becoming a strategic competitive advantage.

Kuehne+Nagel
Trust Semicon Logistics by Kuehne+Nagel to navigate even the most demanding supply chain challenges.

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The 3D InCites Member Spotlight episode features exclusive conversations with industry leaders at IMAPS Device Packaging Conference 2025, exploring the cutting-edge of semiconductor packaging innovation and domestic manufacturing expansion.

• Rex Anderson of Micross details their RESHAPE program funding and Integra acquisition, establishing them as North America's largest domestic OSAT
• Calvin Cheung of ASE explains how advanced packaging enables AI infrastructure while reducing power consumption by 40-60% through vertical power delivery. He also describes silicon photonics emerging as a game-changer for data transmission, using light instead of electrons for faster, more energy-efficient signal integrity
• Keith Felton of Siemens discusses digital twin technology allowing early predictive analysis during package prototyping to prevent costly downstream engineer change orders - or ECOs.
• Vahid Akhavan highlights PulseForge's photonic debonding technology partnerships for clean, high-yield wafer release
• Bernd Krafthoefer and Florian Lechner, ERS Electonic representatives,  share insights on their new European competence center and sub-micron photonic debonding capabilities for 300mm wafers.

Join us next week as we explore supply chain resilience in the semiconductor capital equipment sector with Barry O'Dowd from Kuehne+Nagel and special guest Kamal Aluwalia, CEO of Resilinc. Learn more about member benefits at 3DInCites.com/memberships.

IMAPS Device Packaging Conference
Interconnects for Tomorrow’s Applications

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