One of our most listened-to episodes in Season 1 was on the importance of package design for chiplet integration. For those of you who are new to this podcast and chiplet technology, in a nutshell: Chiplets are hardened blocks of IP of different semiconductor technology nodes that result from disaggregating – literally taking apart a System-on-Chip. These blocks are then reintegrated as a single package using high-speed interfaces to deliver greater performance at a reduced cost, higher yield, and lower power with only a slightly larger area than a heterogeneous integrated advanced package.
Chiplets are big news right now for companies like Intel, AMD, and TSMC – but one of the challenges for broadening the market is the lack of standardized models. To address this, the Chiplet Design Exchange was created.
In this conversation, Françoise talks to Anthony (Tony) Mastroianni of Siemens EDA and Jawad Nasrullah Palo Alto Electron, Inc. to demystify all of this – especially for those who are not fluent in chip and package design.
You’ll get some back-story on the evolution of chiplets, and the importance of standardizing chiplet models and workflows for the chiplet ecosystem. You’ll also learn about the Chiplet Design Exchange, what the goal is, and how you can become involved.
Meet the Speakers
Tony Mastroianni has more than 30 years of experience as an engineer and engineering manager in the global semiconductor industry. In recent years, he has focused significantly on advanced ASIC package design flow development (2.5/3D). He currently leads the development of Advanced Packaging Solutions for Siemens Digital Industries Software. Prior to joining Siemens, he served in engineering leadership positions at Inphi and eSilicon. He earned a bachelor’s degree in electrical engineering from Lehigh University and a master’s in electrical engineering at Rutgers University. Email Tony.
Jawad Nasrullah is a chip designer with expertise in chiplets, microprocessors, HW/SW co-design, and SerDes. Previously Jawad was the co-founder and CTO of zGlue, Inc., a Silicon Valley chiplet startup that set the direction of chiplet technology and developed a number of heterogeneous integrated circuits. Jawad is now working on his next adventure, Palo Alto Electron. Jawad has been very active with the ODSA workgroup within OCP to help catalyze chiplet ecosystems. Before zGlue, Jawad has held leadership positions at Intel, Samsung, Sun Microsystems, and Transmeta. Jawad holds a Ph.D. degree in Electrical Engineering from Stanford University. Email Jawad
The Chiplet Design Exchange is part of the Open Domain-Specific Architecture (ODSA) Sub-Project under the OCP Server Project. Learn more here.