Chip Champions: How The 3D InCites Award Winners Are Revolutionizing Heterogeneous Integration

The 3D InCites Podcast celebrates microelectronics industry innovation with a special episode featuring this year's award winners in heterogeneous integration and chiplet technology.

• SallyAnn Henry, Jim Straus and David Wang, ACM Research, describe a horizontal rotation plating system for panel-level packaging with superior uniformity across square substrates
• Eric Gongora, of MacDermid Alpha, explains how NovaFab fine-grained copper enables hybrid bonding with customizable annealing times and improved electron migration resistance
• Chuck Woychik, NHanced Semiconductors, talks about how the company brings hybrid bonding capabilities onshore with expertise in wafer processing for both defense and commercial applications
• Keith Felton, Siemens Digital Industries Software, introduces Innovator 3DIC for hierarchical device planning that automatically propagates design changes throughout chiplet interfaces
• Kazuyuki Mitsukura explains how Resonac builds collaborative consortia in Japan and the US to solve complex advanced packaging challenges through shared resources
• Rex Anderson from Micross shares his engineering journey and passion for mentoring the next generation of technologists
• Ron Huemoeller and Eelco Bergman discuss how Saras Micro Devices addresses AI power challenges with embeddable S-Tile capacitors. They also talk about Saras corporate culture.

EV Group
EV Groups supplies high-volume equipment and process solutions for semiconductor manufacturing.

KLA, SPTS Division
KLA provides semiconductor equipment for metrology, inspection, wafer processing, and more.

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Transcript

ACM Research: Horizontal Rotation Plating

Speaker 1 0:08

Hi there, I'm Francoise von Trapp, and this is the 3D Insights Podcast. Hi everyone, did you know that each year since 2013, we have celebrated the microelectronics industry's efforts in innovation by hosting the 3D Insights Awards? Now these awards recognize excellence in technology, enablement for heterogeneous integration, 3dhi and chiplets. We also present an Engineer of the Year Award and a Best Place to Work Award and a Best Place to Work Award. So in this episode, we're speaking with this year's winners of all these awards to learn more about their companies and the roles they play in furthering these critical technologies. So my first guests today are David Wong, sally Ann Henry and Jim Strauss of ACM Research. Welcome to the podcast, everybody.

Speaker 2 0:58

Thank you, thank you, thank you.

Speaker 1 1:00

So before I ask any questions, can you each just give me a little bit about your background and your role at the company? David, you're the CEO. Why don't you start?

Speaker 2 1:09

Yes, I'm the CEO of the ACM Research and take care of just the general and management.

Speaker 1 1:16

And you were the founder of the company.

Speaker 2 1:17

Oh, yes, also yes.

Speaker 1 1:19

So how long has ACM Research been in business?

Speaker 2 1:21

The company was founded in 1998 in the Silicon Valley.

Speaker 1 1:25

Okay, all right.

Speaker 3 1:34

And Jim, so I've been working in the industry for more than 30 years. David asked me to come to work for ACM Research about five years ago and we're really enjoying our relationship and enjoying growing the company in some great ways.

Speaker 1 1:43

Okay, and Sally Ann, well, everybody knows me. This is true. We know you outside from ACM Research. I have known you since your days at EKC. Maybe no the next, sez, sez, sez.

Speaker 4 1:58

So I've been in the industry over 40 years in two or three only three or four companies. I've been at ACM now for eight years. I'm now being the chief technologist outside of Asia, supporting the US and Europe.

Speaker 1 2:13

I'm glad to be here, thank you. And last you were on our podcast when we were at IMAPS Symposium and that was your first IMAPS event. That was my first IMAPS yes, last October, okay. And here you are now, six months later, winning an award yeah, okay. So the questions that we asked all of our winners was what current challenge or roadblock to the adoption of heterogeneous integration did you, as a company, see that you knew you could address?

Speaker 2 2:39

Okay, I think. Obviously this heterogeneous packaging needs a lot of high density. So the pitch size has been coming from a few microns down to micron size, even go to future sub-micron. So we see the challenge here. One thing is the copper plating. Today we got us a word and we're using very differential technology. Actually we are using horizontal rotation plating as different from other people playing in vertical plating. The advantage of horizontal plating can give you much better uniformity, much better COP control and for high density. So we believe that will be our ultimate solution for the panel level in square or big size.

Speaker 1 3:26

And Sally-Ann, can you expand on that a little bit?

Speaker 4 3:29

I think with the development we have done, using our existing wafer technology and spinning of wafers for cleaning or coating or whatever application we have, we've expanded that into panel plating using the spinning method horizontally, where we, as david said, we could get very good uniformity across the panel, whether it be 15 by 15 or 600 by 600 for electroplating, and this is what the award was on was on the panel, was on the panel level plating. We have other tools in that that area, but that's not covered in the award?

Speaker 1 4:08

Right, okay, and we're hearing a lot about glass core substrates and glass panels. Does this tool support different substrate materials besides silicon?

Speaker 4 4:19

Yeah, it does. It supports glass and other organic materials. Okay.

Speaker 1 4:25

All right. So what stage is the tool in at this point, jim?

Speaker 3 4:31

So this tool is still in development. We don't have anyone at a customer yet.

Speaker 1 4:36

Okay.

Speaker 3 4:37

But soon, hopefully, we will have a beta site activity and we can actually handle wafers right now and place them in the chamber and demonstrate our capability on the tool today.

Speaker 1 4:53

Are you working with any manufacturing partners to bring the tool up to commercialization?

Speaker 3 4:59

I'll let David answer that.

Speaker 2 5:00

I think we'll work with a few customers to introduce a horizontal. And why? Because horizontal plating they're not only providing excellent uniformity, cop control and more important is you can reduce the cross-contamination between, say, copper bass or the nickel bass or the gold silver bass. That's where we basically get all the benefits horizontal 3-millimeter wafer copper plating benefit. So we believe that will be excellent for the future, this panel-level copper plating solution.

Speaker 1 5:35

Okay. So what's the industry's response been so far, aside from the fact that you won an award?

Speaker 3 5:42

Okay, so I think there's a lot of interest and people are recognizing the requirements for panel processing are going to be more like wafer processing. Things are going to move in the direction of uniformity requirements and defect requirements are going to be much tighter than they have been in packaging operations in the past.

Speaker 1 6:08

So do you see, as a company that initially focused on front-end processes, that now the wafer level is, as you say, starting to require more front-end-like processes?

Speaker 3 6:20

Absolutely.

Speaker 2 6:21

Yeah, I want to see that. Obviously, this panel-level packaging demands a lot of new technology right. Maybe I want to elaborate more about copper plating. If it's a circled wafer, you rotate it horizontally. It's much easier. But if it's a square substrate, if you rotate the wafer, your electric field, which is square too, you have to rotate that electrical field. That's really challenging for this horizontal copper plating. With our innovation-provided technology, we can rotate this square electrical field. That's why I give you a uniform plate on the entire wafer, across the corner, across all areas.

Speaker 1 7:03

Can you accommodate the different panel sizes that are being standardized on, because I know there's two, there's 600 by 610, I think, and then 500 by 515.

Speaker 3 7:13

510 by 515 and 600 by 600. Okay, thank you, I appreciate that.

Speaker 1 7:18

Well, you know why can't they just be 500 by 500 and 600 by 600? What's the 10 and the 15 all about?

Speaker 2 7:24

Well, that's a history of their substrate right? I mean, some companies start as a 515 by 510.

Speaker 5 7:30

That's their history, that's not even square.

Speaker 2 7:32

It's not square, you're right.

Speaker 1 7:34

I mean, and we know that in this industry, even the smallest millimeter, that five millimeters or a 510, yeah, five millimeters makes a difference.

Speaker 4 7:43

I I mean, I know I would go crazy looking at it, our tool is set up that you can run either or the small one or the big one. Okay well.

Speaker 1 7:52

So, coming from front end and into back end, was it a big stretch to develop this tool? Did it take? Was it? Was it not that heavy a lift, considering what you were already working on, to adapt it for panel we?

Speaker 4 8:06

were already doing electrochemical plating anyway, in both in dual damascene, but also in the packaging area for copper, tin, silver, nickel, etc. So we were already doing that in electrochemical plating, so it wasn't that big a jump. Yes, there's a lot of different, more complex things to actually the panel, but in reality it wasn't such a huge jump because we were already working in that area.

Speaker 1 8:36

All right, congratulations again on this award, and where can people go to learn more about?

Speaker 4 8:41

ACM. You can visit us on our webpage, wwwacmrcom, or, if you know who I am, drop me an email at sallyannhenry at acmrcom.

Speaker 1 8:56

And they can probably find you on LinkedIn. They'll find me on LinkedIn too. Okay, and can I put links to your LinkedIn contacts on the show notes? Sure, great, all right. Well, thanks again for joining me today, enjoy the rest of the show.

Speaker 2 9:10

Thank you.

Speaker 1 9:11

Thank you. So my next guest is Eric Gangora from McDermott Alpha. Welcome to the podcast.

MacDermid Alpha: Chemistry for Hybrid Bonding

Speaker 7 9:20

Hey, thank you, nice to be here.

Speaker 1 9:22

Congratulations again on being a Technology Enablement Award winner.

Speaker 7 9:26

Thank you.

Speaker 1 9:27

And can you tell us a little bit about McDermott Alpha and your role there?

Speaker 7 9:32

Sure sure. So McDermott Alpha, you know we're truly a materials company, but we're also material solutions. You know especially chemistry. We provide from solder all the way through. You know dual damascene chemistries for sub-two nanometer. So we have any electronic device that you have with you 99% of the chance that all of our products are in it, whether it be a solder, a flux, a die attach or copper plating, bumping or damascene.

Speaker 1 9:59

So you basically run the gamut of the whole process from front end through back end and advanced packaging and then board.

Speaker 7 10:06

And assembly Assembly. Okay yeah, including IC substrates and PCBs.

Speaker 1 10:10

So for this award, though this is from your advanced packaging line Right right. Nova Fab fine-grained copper. Yep, yep, Okay.

Speaker 7 10:17

The challenges in hyperbonding, besides the operational challenges like speed and capability the operational challenges like speed and capability, From a chemistry perspective, you know it's a challenge to establish a pure chemistry that can function the way that you need it to function. So, if you remember the hybrid bonding, there's a recess right, there's a kneeling time, so different customers have different requests for a kneeling time. So obviously the challenge is to establish a chemistry that bonds well and then from an electric performance perspective also performs well. So we're focusing on that contact right or that hybrid copper-to-copper contact.

Speaker 1 10:56

Because this is not necessarily copper bumps to copper bumps right. Correct, these are just copper pads to copper pads.

Speaker 7 11:01

Yeah, it's a copper pad underneath a resist right, so it actually has a little below the surface and it anneals. So as it anneals, it comes together and you know, one of the speakers said fusing together. But it comes together when you want it. But what ends up happening is different customers want different annealing times, right, okay, they want different times of floor life. So let's say, you know, because some of this is self-annealing, but some customers want it to anneal at a certain temperature, others at another temperature. So it's not just a challenge of creating the chemistry to support the hybrid bonding, it's actually the electrical performance and the processes that each of the customers want. So today, going through qualification, and the challenge is not just the packaging side, it's also electron migration. So we're doing grain engineering, which is tied to material science, where we're trying to structure the grains and set it up so that the electron migration is minimized.

Speaker 1 11:55

Okay, All right. So in the hybrid bonding process the two surfaces have to be super planar, right?

Speaker 7 12:02

Right and super clean. Yeah, pure, pure chemistry.

Speaker 1 12:04

And so your material goes in as part of the manufacturing of those pads.

Speaker 7 12:12

Correct, correct, yeah, it's during the electroplating. So, if you can imagine, instead of a bump, right, you end up playing a pad. That's a couple of microns, right? Okay, yeah.

Speaker 1 12:22

All right, and so then we're putting the two surfaces together. This also for dye to dye, as well as dye to wafer and wafer to wafer.

Speaker 7 12:29

Yep, yep, it's copper to copper, copper to copper. Okay.

Speaker 1 12:31

Yep, and so then they're doing the DBI bond right Yep. Yep. And then the batch anneal.

Speaker 7 12:45

So it's a blast just because there's so many variations. And what you're trying to do is, you know, set up a chemistry, a copper chemistry, based on, you know, the additives that we have, so that it performs a certain way, so it anneals a certain size, so it, you know, anneals at a certain temperature, and what's interesting is every customer has their own solution.

Speaker 1 13:03

Right, okay, can you tune the material based on customer specification?

Speaker 7 13:08

Yeah, that's a challenge For a few years now. Every chemistry, whether it be a bump, an RDL or even something like this, it's all customized to the design and the tool that the customer is using. So, yeah, these are all one-off chemistry solutions. Especially the more advanced they get, it gets even more challenging.

Speaker 1 13:26

But it's all under one product line. Yeah.

Speaker 7 13:28

Okay, yeah, it's under the NovaFab and they have different versions of it.

Speaker 1 13:33

Okay, so what stage is the material at? Are we in commercialization with it already, or is it still in development?

Speaker 7 13:40

The first pass is commercialized. So we're offering it's commercialized. But there are subsequent revisions and optimizations and what you'll find is, with these chemistries you establish a plan of record, but the lifespan of these products is no longer two, three, four, five years, it's six months or nine months. Why? If you go back and look at TSMC's info process right, so we wound up their first POR, but it was six months because they redefined the package and they have a whole new design. So there's a lot of designs that go between six and nine months and the customer comes back and says, hey, we need it to go, you know, faster. Or in this case now with HBM and HBC, it's all performance. You know, speed and cost is a challenge, but more than that, they want to see the performance.

Speaker 1 14:24

So how long does it take to qualify a material into a process generally?

Speaker 7 14:34

If we have a base material, the development can take years. But once it's qualified and we just adjust because it's usually a few additives we adjust the concentration levels, we adjust some of the additives it could be quick once it's qualified as a POR.

Speaker 1 14:41

All right.

Speaker 7 14:42

So every six months you might have to tweak it to a new, a new recipe, or, you know, let's say, a new design comes out where the pitch is different, right? Or it's mixed With hybrid bonding. It's a little more straightforward because you know they're trying to define what the pads are, right. But if we back up to something like copper pillar? No one has a standard copper pillar size dimension. You know, people say between 30 and 50 or 30 and 70, but it's all over the place and each of the customers wants a certain level of purity for the copper. Okay, you know, these solutions are truly unique and customized for the customer's application, the design and then the tool they're using, especially with hybrid bonding. Now, the tool that's used is key.

Speaker 1 15:21

Okay, so what's the industry's response been to this material?

Speaker 7 15:26

We're probably one of the only chemistry suppliers that has a working hybrid chemistry right in production release for commercialization. So the challenge isn't necessarily in our electroplating copper. There's other process challenges that are kind of slowing things down. But from our perspective our copper solution should be what the market POR is. You know, once you get into grain engineering and you establish the grain structure, that's just the next level of technology sophistication. We're doing material science now, not just chemistry. We're looking at the material properties, the purities, the capabilities, the compatibilities.

Speaker 1 16:00

Well, this has been fascinating. Actually, it's something I hadn't really thought of in the past, and I think a lot about hybrid bonding and we talk a lot about hybrid bonding, but I have never drilled down to think about the actual chemistry used for the electroplating process, and that it mattered and that it made a difference. So I just learned something today.

Speaker 7 16:19

Yeah, this is great. Even the C&P process. People have different processes, different customers. You see the requirements coming back to the front end Right, more and more so. Right Even for back-end processing.

Speaker 1 16:29

You do front-end materials, you're able to leverage some of that know-how into the material used in hybrid bonding. Correct yes, it's not really used in hybrid bonding, but it's designed for the pads that will be hybrid bonded.

Speaker 7 16:42

Right, the mechanism and the way we solve the problems. For chemistry right, whether it be a bump, rdl or damascene right, the electrochemistry is pretty much the same right. But once you start getting into what we're doing now, which is grain engineering, we've never had to do it before. Grain engineering, grain engineering, because you're getting down into the.

Speaker 7 17:01

Grain structure. So, for example, we do a one one, one alignment, the grains look like columns, let's say so. What they're trying to do is engineer the grains to minimize the boundaries and minimize electromigration. So instead of just reliability and just speed of performance, they're looking at electromigration, because there's so many of these IO, some of these connections they want to make sure that they can design to it.

Speaker 1 17:26

Well, this has been great, and so congratulations again for winning the award when? Can people go to learn more about McDermott Alpha?

Speaker 7 17:33

So we have a great website that's just being launched. It's being updated, but a lot of that is in the site. I think it's going to be the new website's launching, I think at the end of this month, but they can go on there today. They can find the information. But you know, once the new website comes out, it'll be a lot more.

Speaker 1 17:49

And it's McDermottAlphacom.

Speaker 7 17:51

Yep.

Speaker 1 17:52

Okay, well, thanks again.

Speaker 8 17:54

Thank you for joining, appreciate it, take care Thanks.

Speaker 1 18:01

So I am here with Chuck Wojcik from Enhanced Semiconductors. Welcome to the podcast, Chuck.

Speaker 6 18:06

Hey, thank you very much. Nice to be here.

Speaker 1 18:08

Now, you were here last year accepting an award for Enhanced for Best Place to Work. Is it still a good place to work?

Speaker 6 18:14

It's a great place. I really enjoy it and I know other people do too.

Speaker 1 18:18

And you're still there.

Speaker 6 18:19

Yep, I'm still there.

Speaker 1 18:22

So tell me a little bit about your role there.

Speaker 6 18:24

So my role right now my title is VP of Business Development, so I talk with a lot of customers about future opportunity and I work very closely with Bob to grow the business. So we're really looking forward to bringing this really onshore, so advanced packaging.

Speaker 1 18:41

No, so you guys are going full steam ahead.

NHanced Semiconductors: 3D Hybrid Integration

Speaker 6 18:45

Exactly, and what's interesting is, the more we talk with customers, the more we find that they want this onshore. But, as you know, what we're doing is looking at the next generation of packaging and, as you know, we're focused heavily on hybrid bonding wafer to wafer, die to wafer, along with interposers, both silicon and glass.

Speaker 1 19:07

Okay, so you're here because you won a technology enablement award this year from 3D Insights. Congratulations.

Speaker 6 19:16

Thank you very much.

Speaker 1 19:17

So I know that part of the application process was to answer some questions, and the main one was what current challenge or roadblock to the adoption of heterogeneous integration did you, as a company, see that you knew you could address?

Speaker 6 19:32

Yeah, that's a really good question. The technology drive today is really disaggregation of the dye, and this really gets into what everyone's saying is you know, moore's Law is kind of losing steam here. So what is happening? You're taking that large dye and breaking it up into cells. We call those cells chiplets. Now some of those cells, to perform better, need to be shrunk. So you need to go to a finer node. And why that makes more sense? Because now with a finer node you can get a higher yield and, as you know, when you start getting 20 nanometer and less, you don't have the cost advantage anymore. So you can shrink where you need to. But a lot of those cells or chiplets you don't want to shrink because when you shrink them the performance degrades. So this is where it's really good to now integrate at the packaging level, particularly the silicon interposer.

Speaker 1 20:23

Okay, so the technology that got you the award was around 3D hybrid integration, so what does that mean?

Speaker 6 20:32

It's a really good point because now, if you look at scaling, the pitches are always going to get smaller and smaller. So when you start dealing with 10-micron pitch and below, this is where hybrid bonding is really important, because it's a technology that's able to scale for finer and finer pitches and solder loses steam. So the beauty of hybrid bonding, particularly a dyed wafer, is that once you develop it, you can keep up with the advancing nodes, particularly the finer nodes, as they scale. So you have a technology that has a long life in it. And that's where we see this is a great advantage in enhanced right now, because really this is the future and what we see is bringing this advanced hybrid bonding technology onshore, continuing to improve it and maintain it in the US.

Speaker 1 21:21

And you're doing it with mixed materials, right?

Speaker 6 21:25

Correct, we can do it with silicon, carbide, gan, other materials as well as with silicon. So the beauty is it's flexible for many different types of materials, and then we can integrate on this platform, being either silicon or glass.

Speaker 1 21:38

Okay, so now, what stage is the new development around the mixed materials in?

Speaker 6 21:45

So Enhanced has decades of experience dealing with this. A lot of the employees in Enhanced they've been employees coming from the Ziptronic stage, so they understand hybrid bonding. They understand the process details of how to process the wafer to ensure a good yield Because, as you know, to do this it's going to be proper CMP wafer processing. But then also we're working with leaders in the equipment tooling, such as Bessie. So at Enhance right now we have the latest Bessie tool for diodal wafer binding. So the combination of the latest tool from Bessie, coupled with our experience in hybrid bonding puts us in a very good position to be really a leader in this capability in the US.

Speaker 1 22:31

So how is the industry responding to this?

Speaker 6 22:34

It's very positive. We talk with a lot of customers and I think that's part of my job right now is understanding the customers and what they need, and you can see that customers need this advanced hybrid bonding technology and what's also amazing is they want to see these suppliers, such as Enhance onshore.

Speaker 1 22:54

You're here at IMAPS and have you been talking to a lot of people about what you're doing.

Speaker 6 22:59

I talk with many people about what we're doing. I talk with many people about what we're doing and what's interesting now is I think Bob Patty, my boss, the CEO, has a really good reputation. So whenever I tell them I'm from Manhattan, they go oh, yeah, yeah, we know Bob very well. So the words out there about Bob and the capability and I think the fact that we're doing this and we're really a growing business is getting a lot of these guys very excited. So we're heavily involved with defense industrial base, but part of my job right now is to help grow the commercial business and it's interesting to see the opportunities out there for us.

Speaker 1 23:36

What are the opportunities in the commercial space?

Speaker 6 23:38

One particular thing we're seeing right now is a domestic supplier for interposers and, as I mentioned before, we have the capability to do silicon interposers. And then we also have a partner, mosaic, to work with on glass.

Speaker 1 23:54

Okay, so Mosaic is also a 3D Insights member. I love it when I hear the members are working together on projects like that.

Speaker 6 24:01

Yes.

Speaker 1 24:02

Yeah, that's great. Well, thank you so much for joining me today and congratulations again on the win.

Speaker 6 24:08

Well, thank you very much. Nice to be here.

Speaker 1 24:14

So my next guest is Keith Felton from Siemens Digital Industries Software. Welcome back to the podcast, Keith.

Speaker 5 24:22

Thank you, francoise, I'm glad to be here.

Speaker 1 24:25

I think that Siemens has won so many awards with 3D Insights that, yeah, we've done this before, haven't we?

Speaker 5 24:32

We have, yes, and I decided to give it a break for a couple of years. But we had a new product that we launched last year and you know that I decided I would submit that to see what your panel of expert judges thought about it.

Speaker 1 24:45

Yes, and then your colleague submitted one as well.

Speaker 5 24:49

I know, and we beat him out, and I haven't discussed that with him at all.

Speaker 1 24:54

He actually said that you were a worthy opponent, but he was glad that there was one product from Siemens that he wanted, and it's not like you were only competing against yourself. There were some other nominees in there. So first of all, we had everybody fill out an application and one of the questions we asked was what current challenge or roadblock to the adoption of heterogeneous integration did you, as a company, see that you knew you could address?

Speaker 5 25:22

well, one of the things we've been working on was what we call hierarchical device planning, which is actually how you design the interface from the chip. But this is the physical interface, so that's from your micro bumps down to the rest of the package assembly. And you know a lot of people have typically used spreadsheets to do that, which are very static, and you know a lot of people have typically used spreadsheets to do that, which are very static, and you really want to be able to design that at the same time as the chiplet is being designed. So we partnered and we actually did a paper on this that you we would have sent you right, we partnered with intel to actually work on this hierarchical device planning with what we call active pin regions, and so he came up with a methodology and process that lets you very quickly develop your pin bump field and the assignments of that pin and bump field down to the package, and do that in a manner where you can also iterate it very quickly.

Speaker 5 26:17

You know, in the past people, as I said, have used spreadsheets. Right, the problem with spreadsheets is there's no ECO mechanism. With a spreadsheet, someone makes a change, you have to hand edit the whole spreadsheet. We do that all as a digital twin model, so if you make a change it instantly updates and you know exactly where you are. So we enable very fast chiplet bump planning.

Speaker 1 26:38

And the name of the product is Innovator 3DIC bump planning and the name of the product is innovator 3d ic and from what I read, you span from die to package to board to board.

Speaker 5 26:49

Yeah, the system itself has unlimited levels of hierarchy, so you can start at a chiplet level, or even a piece of a chiplet, and then go all the way down to the printed circuit board, the the system's design itself. There's no limit to the levels of hierarchy of interconnect or substrate technology that's mounted on top of the next substrate.

Speaker 1 27:11

And this is specifically designed for chiplet integration.

Speaker 5 27:14

It's designed for heterogeneous integration. Whether they're chiplets or ASICs, it really doesn't care. It's really designed for when you've got multiple pieces of silicon that you need to connect together and place them in a high performance package whether that be an interposer or something like an absolix glass package in order to get your finished component so let's say you've got all of this system all designed and you make a change somewhere in the process, like at the die level.

Speaker 1 27:45

Is it going to automatically update all the way through and make those changes? Because you were talking about how you have to do it manually. So you make one change to, let's say, the die pitch or something.

Speaker 5 27:57

Yes.

Speaker 1 27:58

Is that an example?

Speaker 5 28:00

That's a simple example, right? So you see, you go in there and say, okay, I've defined this chiplet to have a bump pitch of a certain ratio with a certain bump size, and then the ic team doing the digital implementation of the die say, well, okay, we need to change the bump pitch because we've just used, um, let's say, you've used a uh, some ip, an ip block from alpha wave semi, and it requires a different bump pitch because we've just used, let's say, some IP, an IP block from AlphaWave Semi, and it requires a different bump pitch because we changed the IP provider. So they say, okay, the bump pitch has now changed. When they send us that updated information, it automatically propagates through the digital twin model. Everything is updated automatically. You don't have to do anything, you have to read in the information from the chiplet design team and it completely goes throughout the system.

Speaker 1 28:45

Okay, that's really exciting. It saves a lot of time.

Speaker 5 28:49

I would imagine that's what it really does save, because the chance of making a mistake having to physically implement it at each level, the change is huge. And then you have to go through a lot of DRC and LVS activity to make sure that you have actually done it correctly. Our system, innovator 3DIC, pushes it through automatically.

Speaker 1 29:08

Okay, so what stage is this tool in currently?

Speaker 5 29:13

Okay, so it first became publicly available last year in September, so that was its first release. Before that we have had it in beta and alpha phases with our development partner, Intel, so it's been available for a while. But it became commercially available in September last year and in fact we have a new revision of it that is going out in April this year.

Speaker 1 29:36

Okay, so will you be announcing that?

Speaker 5 29:39

The release is called 2504. Okay, and we are looking at possibly announcing that at the Design Automation Conference.

Speaker 1 29:47

Okay, and what would the difference be between the current version?

Speaker 5 29:52

So the new version. We've introduced some new machine learning capabilities into it as well as we have got full 3D blocks compatibility. So those are the two of the biggest areas. The next area after that is integration with Calibre 3D Thermal. So that was a tool that was launched at DAC last year, which is a 3D thermal tool that does both die, stack, die chiplets and complex package assemblies. So we have integrated that technology indirectly.

Speaker 1 30:22

I know there's. One of the things with chiplets is having the common interface and there's different interfaces and one of the ones I know that Siemens works with is the Universal Chiplet Interconnect Express.

Speaker 5 30:33

Yes.

Speaker 1 30:35

Does it function also with others? Does it matter which interface you're using?

Speaker 5 30:39

Well, at this level, the tool is looking at the physical connectivity. It's not really looking at the interface protocol itself. So, yes, we do work closely with UCIE. And now, of course you may have seen, siemens has just signed an exclusive OEM agreement with AlphaWave Semi, so we now have access to all the AlphaWave Semi IP and one of their top ip offerings is ucie. Okay, so we are fitting that into our technology, building default models for that technology into our products, including innovator 3d ic.

Speaker 1 31:14

okay, because intel. You said you developed this with intel. Yes, and they work with aib, right that's, that's right.

Speaker 5 31:20

So they use AIB, but AIB, they offered that to the general public as a general interface format. But, as you said, most people now are looking at either UCIE or Bunch of Wires which comes from the Open Compute Platform.

Speaker 1 31:36

Group.

Speaker 5 31:37

And there are some companies out there that actually have IP that actually will use both UCIE and Bunch of Wires, Blue Cheetah, for example. They have IP that is compliant with both of those.

Speaker 1 31:50

So what has the industry's response been, besides winning this award?

Speaker 5 31:55

So actually it's been very good. I mean, when we launched the product at DAC, we got a huge amount of inquiries about the product. I mean, when we launched the product at DAC, we got a huge amount of inquiries about the product. And with the sudden meteor I won't say sudden, but you've seen an acceleration in interest in heterogeneous integration and a lot of it is. People are still learning, but they're excited to learn. There's an enormous buzz. So we're getting a lot of customer interactions, mostly people wanting to do evaluations and benchmarks, but they need an EDA tool to let them explore their opportunities for heterogeneous integration and that's what Innovator 3DIC does. It's a prototyping planning tool for exploring design scenarios.

Speaker 1 32:35

Okay, well, congratulations again on winning yet another 3D Insights Award.

Speaker 5 32:40

I know Our cabinet is filling up with your awards, but we get a new design last year and this year, right it's pretty right, it's round.

Speaker 1 32:46

Yeah, I don't know what we were thinking before. I really really like this design.

Speaker 5 32:49

I do. It's very nice, it's very heavy.

Speaker 1 32:51

It's very heavy, but it's one piece instead of two pieces.

Speaker 2 32:55

That is true.

Speaker 1 32:57

So where can people go to learn more?

Speaker 5 32:59

So they can go to the Siemens EDA website and look into the IC packaging area, and then you'll find all the information there about not only Innovator 3D IC. You'll also find information there about the caliber technologies that we integrate with, as well as all the information around 3D blocks. Even though 3D blocks is now an IEEE standard it's P3537,. Our website has a whole host of information there, including downloadable examples of 3D blocks that works with Innovator 3DIC, so it's a really good educational area to find things.

Speaker 1 33:34

Great, okay, well, thanks again for joining me.

Speaker 5 33:36

Thank you.

Speaker 1 33:41

My next guest is Mitsukura Kazuyuki from Resonac. Welcome to the podcast, Mitsukura.

Speaker 9 33:46

Thank you.

Speaker 1 33:47

So Resonac was one of our Technology Enablement Award winners and actually they won a special award for a consortium. Can you tell me a little bit about Resonac and your role there?

Speaker 9 33:58

Okay, Resonac is a material company, so we have many line up of the materials for back-end packaging process, such as molding, compound, capillary underfill and also RDA related material. And also we have the substrate core material organic core, solid resist, dry film resist.

Speaker 1 34:16

So I wanted to congratulate you again on winning.

Speaker 9 34:19

I appreciate it.

Speaker 1 34:20

You kind of had to go through an application process to win this award, and one of the questions we asked was what current challenge or roadblock to the adoption of heterogeneous integration did you as a company see that you knew you could address?

Speaker 9 34:33

Yeah, key topics for heterogeneous integration roadmap are vertical and lateral high-density interconnection and border-level reliability of the large package. In case of that, we need many material and many process like bumps and interposer material, packaging, substrate, rdl, solidologies, underfail molding compound Many process and material is required. The fail molding compound many processes and materials are required. So, in case of that, if only one company cannot have the solution to have the test vehicle and to better hold the better material and better equipment, so that's why we need to collaborate with other companies.

Speaker 1 35:21

As a materials company, you saw a need for collaboration with equipment suppliers and manufacturers in other parts of the ecosystem, so it was really your initiative that started to build the joint consortium.

Speaker 9 35:36

Yes, that's right.

Speaker 1 35:37

Okay, so can you tell a little bit about Joint, Because you have two phases right? There's Joint in Japan and then there's Joint 2.

Speaker 9 35:46

We have the Joint 1. Okay. That is our first one. We started the consortium in Japan, okay, and now moved to Joint 2. Okay. Joint 2 is supported by Japanese government and that's why only Japanese company join.

Speaker 1 36:02

Who are the other members of?

Speaker 9 36:04

Joint2? The same equipment company as well, the Disco EWARA, and also the plating company Uemura, and also the substrate company Shinko and DNP. Okay, so what made you decide to duplicate that in the US? Because the target is completely different. So join to focus on the R&D. So this is like us we would like to share the test vehicle for the better material and better equipment and better substrate. So this is like an internal R&D activity. So US Joint is focused on the customers. So customers bring their feasibility study items into US Joint. So US Joint is completely customer-oriented project.

Speaker 1 37:03

Okay, and so joint two was all for R&D.

Speaker 9 37:07

Yes.

Speaker 1 37:07

And then the joint US is focused on the customer. So, joint two is only Japanese companies and in joint US how many companies do you have, and are some of them US companies?

Speaker 9 37:23

Yes, now 12 companies, US and Japanese companies.

Speaker 1 37:28

Is it all the same joint two companies plus US companies, or is it a different group?

Speaker 9 37:33

Different group because the location is different, so we picked up the different companies.

Speaker 1 37:42

Okay, so what stage are these two consortia at at the moment?

Speaker 9 37:49

Actually, joint 2 is a five-year project and half of five years was passed, and the US Joint is under construction and the opening target is this October.

Speaker 1 38:02

Okay, so what's been the industry response to this?

Speaker 9 38:06

They are very interested in utilizing this capability because our target customer focuses on the packaging design, but there are no capabilities in the United States, so that's why they want to collaborate with us. And joint two we have the certain target like a fine-band pitch interconnection below 10-micrometer pitch and also the one-by-one RDL, one-by-one line space for RDL, including dual-damaging process. And the third one is a large package including the border-division process. And the third one is a large package including the border-level reliability. We have plenty of data from Joint 2, and we have the technical presentation and also we have the presentation in a major conference.

Speaker 1 38:57

Okay, is there a partnership between Joint 2 and US Joint?

Speaker 9 39:00

Yes.

Speaker 1 39:00

Okay Now. My understanding is that there was no CHIPS Act funding involved at all. Because you didn't want to wait that long.

Speaker 9 39:08

First one is the timing.

Speaker 1 39:09

Yeah.

Speaker 9 39:09

Second one is the regulation.

Speaker 1 39:11

All right, well, congratulations again, thank you. And thanks for joining me on the podcast. Okay, thank you.

Speaker 10 39:28

so my next guest on this episode is our engineer of the year rex anderson.

Speaker 1 39:30

Welcome to the podcast, rex. Hello, thank you, so good to have you here. You know we didn't have an engineer of the year last year oh, so I'm the first, I guess we've had them before there were no nobody got nominated last year. I guess nobody fit the bill, but this year we had quite a field. So can you talk a little bit about your background and your role at Micros?

Speaker 10 39:46

Sure. So it was kind of a winding path to get to advanced packaging. I mean, there's not a lot of people that say, hey, this is what I want to do out of school. So I went to the University of Michigan. I was in the nuclear engineering department and fortunately I had two professors that were in plasma physics, mary Brake and Ward Getty, and you know, that's where I got introduced in the kind of semiconductor field. So I was recruited out of there into Silicon Valley with Applied Materials. I was in a photomask etch group there, loved it, did a lot of optical emission spectroscopy, developed hardware for them, got to travel quite a bit, made my way back to a startup company where I I'm not sure we're going to meet payroll next month and I said, oh, what a coincidence, I don't think I'm going to be here next month either. So I went home, got on Monstercom emailed from my Hotmail account and waited for it.

Speaker 1 40:55

What was this? Is this in the 90s?

Speaker 10 40:57

A little bit after that, but close to it, I got a call from a company called Unitive. Their HR department called me on my landline and fortunately got the interview and got the job. So I worked in the disruptive technology group that's in the Micross building today.

Speaker 1 41:16

Wasn't Unitive acquired by Amcor.

Speaker 10 41:18

They were yeah. So Amcor acquired Unitive. Shortly after that, the acquisition was complete, and that's how Amcor got their bumping technology Okay, and so our group the MCNC group, you know still was able to practice that same technology that they were using, and that's what Micros is using today. I mean, obviously Amcor has made some improvements, and so have we over the years, but that's what we're doing today.

Speaker 1 41:44

So were you part of before Micross, the AIT group was part of the RTI.

Speaker 10 41:50

Yes.

Speaker 1 41:50

So you joined that team.

Speaker 10 41:52

I did.

Speaker 10 41:53

I joined that team and John Lannan and I and one of our other colleagues carved that group out of the Research Institute and one of our other colleagues carved that group out of the Research Institute and that was really sparked by at the time I guess that would have been about 2015 or so when the acquisition of Flipchip International was purchased by a Chinese company. So we had a lot of folks in the dib panic about where they were going to get their bumping done and the only place really they could go to was this small research group in Research Triangle Park, north Carolina. And so, fortunately, you know we talked to the Institute and you know we saw our value at that time and we shopped ourself around and Mike Ross was a great fit that time. And we shopped ourself around and Mike Ross was a great fit. They were serving the same markets we do and we filled that void and that hole that they needed to finish out a turnkey solution. So they're one source, one solution. They had test and assembly, but they didn't have the wafer level packaging and that's what we're doing today.

Speaker 10 42:54

Okay, yeah.

Speaker 1 42:56

So what gets you out of bed every morning?

Speaker 10 42:59

Well, the first thing is, you know, a gratefulness to my Lord to do what we do. I mean, how exciting is it to be in advanced packaging right now? Secondly, the work ethic that my mom and dad instilled in me to get out of bed. But then there's a there is a sense of duty to the market. That we serve is to keep the American warfighters safe, our allies as well and then also to enable high reliability technologies and medical devices and space exploration. That in itself, how cool is that and how rewarding is that to be a part of that.

Speaker 1 43:34

And so what keeps you awake at night?

Speaker 10 43:37

Well, you know I could talk about because I was one of the guilty parties of, you know, letting this technology go overseas and you know the fact that we let a lot of innovation leave the country. But you know, I'm confident we're going to bring a lot of that back. I think we're making the right steps to do that. One thing that does kind of keep me awake at night, that I've observed throughout my career, even in Silicon Valley, is that we work on a lot of important things, but this isn't the most important thing. You know, work-life balance shouldn't be a catchphrase. We're all in this together as a marathon. This isn't a sprint. Our relationships with our family and friends are important. You know I'm a Christian. That's how I'm. I stay, you know, based and I have peace in my life from that. So I hope the same for others. But I think it's really important that we all see what we're doing as important, but it's not the most important thing.

Speaker 1 44:25

So what do you find most rewarding about your work?

Speaker 10 44:28

For me, the solutions that we come up with in advanced packaging every day. It requires so many different disciplines. In our group we have chemists, we have mechanical engineers, electrical engineers, so it really stimulates the engineering scientists inside you. So you have to have a good balance of that. Whenever we are able to sit down and brainstorm for these solutions, that's like the highlight of my day, and the people that I get to work with that's the biggest reward. You know, like at this conference here, there's so many brilliant folks here. But even at our group at AIT, we have this bimodal distribution of folks that I've been working with for a couple of decades. But then we have these new engineers and scientists coming in that we've been able to develop, that have all these fresh ideas. Isn't that fun? That's the funnest part. Oh, that is the funnest part, absolutely.

Speaker 1 45:23

We've been bringing some newcomers into writing. At 3D Insights. I have a couple of interns who are getting their degrees in international studies. I've got our new managing editor, jillian, and I felt like the industry had a lot of older people writing. We didn't have a new crop of technology writers. I would agree that some of the most rewarding thing is working with the young people and seeing them all get all fired up about what we're doing.

Speaker 11 45:45

Absolutely.

Speaker 1 45:46

So you're talking about work-life balance, but you go outside a lot of just your general workday to contribute. I mean, that's really what won you the award was your participation in industry activities, industry events and your mentoring. So what would you consider to be your greatest contribution to the engineering profession and its communities?

Speaker 10 46:07

I think that's what you touched on. If you stopped anyone in this room and asked them why are you doing what you're doing? Most of them would probably point to a teacher, to an aunt, to a mom, a dad that encouraged them to be in science and math and or pursue engineering. You know we go to these conferences and we hear about workforce development. That is not an HR problem, that is our problem as engineers and scientists. We need to be actively going out there and encouraging students with our time, with our efforts. If you think about it, nowadays and it's been this way for a while kids are bombarded with social media, tv and movies about entertainers, lawyers or just medical doctors and the engineers and scientists get kind of lost in there and the perception of what does an engineer or scientist do and what kind of fields and opportunities it's just complete mystery to most kids. So it's really important that we all go out and do that.

Speaker 1 47:10

I mean, there's some of the biggest users of our technology, but they want to design apps. That's right. That's because apps are cool, but we have to teach them that designing the chips that makes the apps possible is also equally cool.

Speaker 10 47:24

I have two daughters at home, so one of the things that my wife and I have always been hypersensitive to is to making sure that STEM is encouraged, and females too, because it's underrepresented population and other minorities as well. She's been kind of my standard, Actually. She just started a HOSA group with all girls. We've coached an all girls robotics Lego team, so those are just examples where, again, it just takes a little bit of time on all of our parts. As long as we can influence a couple more people in your life, then you've replaced you and someone else right, oh, good point.

Speaker 1 47:56

Well, congratulations again on your Engineer of the Year award. We're really happy to present that to you and we look forward to seeing what's next.

Speaker 10 48:03

Thank you so much.

Speaker 1 48:09

So my last guests of the day are Ron Humuller and Ilko Bergman from Saris Micro Devices. Welcome to the podcast, guys.

Speaker 8 48:17

Yeah, thank you very much. Thanks, francoise, happy to be here.

Speaker 1 48:20

So you are the winners of not one, but two 3D Insights Awards this year. You've got a Technology Enablement Award and you've got Best Place to Work Congratulations.

Speaker 6 48:31

Yeah, thank you.

Speaker 1 48:33

So, before we talk about why you got selected for the Insights Awards, can you tell me a little bit about yourselves and your role at Ceres?

Speaker 11 48:41

Sure. So this is Ron Humoler. I'm the CEO of Ceres Micro Devices. I've been here for a couple years a little over two years now. I started actually prior to Ceres Micro Devices. I was working at Ampore Technology for about 25 years. The last five to six years I was their CTO and then I went on to Applied Materials for a couple of years to help them start up part of their packaging business there, and then now from there to Sarah's Microvices as CEO.

Speaker 1 49:09

Now? Are you one of the founders or did you join as?

Speaker 11 49:13

I joined after, so the founders were Venky Sondranan. Oh yeah, venkei, I know, benkei, I didn't know that he was one of the founders of CERA. Yeah, so yeah, Benkei had the original idea it's his concept and then he spun it out and KCK picked it up from Novellus and Benkei Okay, and then brought both Elko and I on after that Okay, great.

Speaker 8 49:40

And Elko your role. I'm the chief business officer and I also joined about two and a half years ago, so I'm doing the customer development side and the commercialization.

Speaker 1 49:47

Right, and so you were in stealth mode for a while. But you've been out of that for a while and I think you won a Startup of the Year award a few years ago.

Speaker 11 50:00

We did, yes, we did Okay.

Speaker 1 50:02

So now your technology is out there and you won an award for it. So what current challenge or roadblock to the adoption of heterogeneous integration did you, as a company, see that you could address?

Speaker 11 50:13

Well, the power equation, the power performance equation. It's paramount to what's going on in the industry today. So you hear a lot of talk about artificial intelligence and how do they bring that forward, especially through the packaging piece, the packaging portion? Well, as they integrate a lot of dye into one package portfolio, managing the power was sort of overlooked and we acknowledge or recognize quickly that that's a piece that needed to be addressed and addressed quickly. The portion of that that we're addressing is through the capacitor today, eventually capacitor and inductor but we're trying to affect the amount of power that is required to operate products and make it more efficient in the process, getting closer to the source, so less waste, just overall better performance per watt.

Speaker 1 51:02

Okay, and so the product is the S-Tile or is it Style?

Speaker 11 51:07

It's Style, it's Style. Yeah, it's Style.

Speaker 1 51:10

So this is your first product.

Speaker 11 51:12

That's correct.

Speaker 1 51:12

Do you have others in the works?

Speaker 11 51:14

We do. We have a fairly decent roadmap laid out at this point. The initial product, which is a capacitor-based product in the style format, will be followed by introduction of inductors and then eventually voltage regulation and other things will follow that as well in the power performance arena power modules, for example.

Speaker 1 51:35

So, and this is going to help address some of that power demand of AI devices, that's correct.

Speaker 8 51:43

Yeah, it's really about how do we help improve the power delivery path, right? So today you hear a lot about the power of these devices, as Ron said, and the power keeps increasing, but the board sizes are fixed. But the board sizes are fixed, and so the power modules need to keep outputting more power, and the power comes in laterally today, so there's a lot of losses associated with that. So, in general, there's a movement towards splitting that strategy, where you still have a two-stage approach for power conversion, but some of that power comes from directly below. They call it vertical power delivery, but what that means is you need to put some of the output capacitors, and other components need to sit between that power stage and the die. So thus the ability to embed is paramount, and our styles are specifically designed for embedding in a packaged substrate or a PCB core, so we go right in the core layer.

Speaker 1 52:46

So how big are these things?

Speaker 8 52:48

So the capacitor elements themselves. We can tune the thickness to match the substrate core thickness so we can offer more or less capacitance based on that thickness. And then dimensionally, the smallest XY today is four by four millimeters. But when we embed them into the tiles, we can configure those tiles in a custom fashion, so they could be rectangular, they could be square, they could have different capacitive fields in different areas, located exactly under the die where the customer needs it Okay, so they're going in PCB, but they also can go into a package substrate.

Speaker 8 53:26

The original goal was to make them embeddable in this package substrate core and now we're also seeing interest in embedding into the PCBs that sit below the package.

Speaker 1 53:37

What about glass core?

Speaker 11 53:39

It could also same thing.

Speaker 1 53:40

Same. Thing.

Speaker 11 53:40

Yeah, we treat all cores, glass, silicon, we treat them all the same and, by the way, because this is configurable, they can be as large as customers want to put as much passive elements in that structure as needed to service very, very large products.

Speaker 1 54:00

So what stage is the product in now?

Speaker 11 54:04

Coming out of the development stage and the pre-manufacturing. So we have multiple lines that we're setting up. We have 5,000 square feet of clean room space. We're operating right now in Chandler for manufacturing.

Speaker 1 54:15

Right.

Speaker 11 54:16

We have another 5,000 in Atlanta we are using for development. We're in the process of adding another 10,000 this year just for manufacturing expansion. So by end of this year we'll have roughly 15,000 to 20,000 square feet of available space to us for manufacturing.

Speaker 1 54:35

Wow, that's really exciting.

Speaker 8 54:37

And from a product side, we've already started shipping engineering characterization samples of the capacitors. Some lead customers are evaluating those and by the end of this year we'll be starting to ship qualification samples as we engage in actual product road.

Speaker 1 54:54

Okay, so what's the industry's response been? It's interesting.

Speaker 11 54:59

Our journey to begin with is largely unknown to our customer base. We had to go out and there's a lot of door knocking and pushing in the first year or so, but since the middle of last year there's been a lot of pull. So now we're seeing customers come to us. People are starting to understand what we're doing, where we're at, what we've been able to produce to date. We've built samples, tested samples, put them in customers' hands and as the information starts to leak out, as we're starting to seed, we're getting a lot more positive feedback. So the customer pool is now starting to come to us.

Speaker 1 55:32

Okay. Well, that is super exciting and I'm really happy for you guys because I've been kind of watching it grow and the fact that you're right here in our backyard in Arizona. So Saris has two locations, in Georgia and in Arizona, and your employee base is what about 40?

Speaker 11 55:52

A little over 50 people 50 people.

Speaker 1 55:54

Okay, so you won best place to work, and this was an online vote. The winner was based on a percentage of the total employee base, realizing that smaller companies competing with companies that had tens of thousands of employees. If we just went with the most people, it would kind of leave the smaller companies out, but you had, I think, 110% of your employee base.

Speaker 1 56:20

So even people who used to work for you, or people who know about you that know you're a good place to work, voted for you. So what makes Sarah's, in your opinion, such a great place to work?

Speaker 8 56:29

Personally, I think this award really belongs to the employees, because they are the ones who create the culture we have. We provide the facilities, the place to have that, but really we have a great culture. We've got a fantastic team in both locations. They work hard, they like to have fun. They have a lot of employee engagement activities that they themselves organize. You know, there's always some sort of monthly event, whether it's a Smash Brothers tournament or you name it, but it's yeah, I think the employees own this one because they're the ones who really help create this environment.

Speaker 1 57:11

Well then they would probably say they couldn't create the environment if you didn't provide them with the resources to do that right. So you've got to take a little bit of the credit.

Speaker 11 57:20

We do a lot of employee check-ins to make sure that the climate, the environment they're operating in, working within that it's a good environment, that they're happy, they have what they need. We like to check the pulse regularly and then we make sure we reward along the way. So we provide lots of opportunities patent harvesting awards, recognition awards. We have bonus program. We have very nice health coverage. We survey the employees, find out what's important to them and we make it important to us.

Speaker 1 57:52

Right, okay, that's great. Do you have somebody who runs the corporate culture?

Speaker 11 57:57

We do. We have a corporate culture committee.

Speaker 1 57:59

Okay.

Speaker 11 58:00

It's a group of people that get together and again they pulse, check what's important, bring it to the executive team and then we work on implementations from there.

Episode Wrap-up

Speaker 1 58:10

I've been to your office and I think there's some really fun spaces to let off steam and do some gathering. It looks like a cool place to work Well, they are literally tearing the show down around us, so I think we're going to have to call this one a day, but I'm so happy to have had the chance to talk to both of you again.

Speaker 11 58:31

Thank you very much for the recognition You're very, very welcome and congratulations.

Speaker 8 58:34

Yeah, our thanks to you and also to the technical committee who helped select us for that award. It's really appreciated.

Speaker 1 58:42

And your employees.

Speaker 8 58:43

Thank you. All right, take care. Bye-bye.

Speaker 1 58:50

Next time on the 3D Insights Podcast, learn how acoustic inspection is becoming a key tool in the semiconductor wafer and package inspection toolbox. As we talk to Brian Schachmuth of Norton Test and Inspection, there's lots more to come, so tune in next time to the 3D Insights Podcast. The 3D Insights Podcast is a production of 3D Insights LLC.